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| HSP50016 TM Data Sheet September 2000 File Number 3288.7 Digital Down Converter The Digital Down Converter (DDC) is a single chip synthesizer, quadrature mixer and lowpass filter. Its input data is a sampled data stream of up to 16 bits in width and up to a 75 MSPS data rate. The DDC performs down conversion, narrowband low pass filtering and decimation to produce a baseband signal. The internal synthesizer can produce a variety of signal formats. They are: CW, frequency hopped, linear FM up chirp, and linear FM down chirp. The complex result of the modulation process is lowpass filtered and decimated with identical real filters in the in-phase (I) and quadrature (Q) processing chains. Lowpass filtering is accomplished via a High Decimation Filter (HDF) followed by a fixed Finite Impulse Response (FIR) filter. The combined response of the two stage filter results in a -3dB to -102dB shape factor of better than 1.5. The stopband attenuation is greater than 106dB. The composite passband ripple is less than 0.04dB. The synthesizer and mixer can be bypassed so that the chip operates as a single narrow band low pass filter. The chip receives forty bit serial commands as a control input. This interface is compatible with the serial I/O port available on most microprocessors. The output data can be configured in fixed point or single precision floating point. The fixed point formats are 16, 24, 32, or 38-bit, two's complement, signed magnitude, or offset binary. The circuit provides an IEEE 1149.1 Test Access Port. Features * 75 MSPS Input Data Rate * 16-Bit Data Input; Offset Binary or 2's Complement Format * Spurious Free Dynamic Range Through Modulator >102dB * Frequency Selectivity: <0.006Hz * Identical Lowpass Filters for I and Q * Passband Ripple: <0.04dB * Stopband Attenuation: >104dB * Filter -3dB to -102dB Shape Factor: <1.5 * Decimation Factors from 32 to 131,072 * IEEE 1149.1 Test Access Port * HSP50016-EV Evaluation Board Available Applications * Cellular Base Stations * Smart Antennas * Channelized Receivers * Spectrum Analysis * Related Products: HI5703, HI5746, HI5766 A/Ds Ordering Information PART NUMBER HSP50016JC-52 HSP50016JC-75 TEMP. RANGE (oC) 0 to 70 0 to 70 PACKAGE 44 Ld PLCC 44 Ld PLCC PKG. NO. N44.65 N44.65 Block Diagram 16 DATA CLK OUTPUT FORMATTER OUTPUT Q Q HIGH DECIMATION FILTER LOW PASS FIR FILTER I I HIGH DECIMATION FILTER CONTROL COS SIN LOW PASS FIR FILTER IQSTRB CLK CLK R CLK 4R OR CLK 2R IQCLK COMPLEX SINUSOID GENERATOR TEST ACCESS PORT/CTRL TEST ACCESS PORT CLKSER 3-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000 HSP50016 Pinout GND 44 LEAD PLCC TOP VIEW IQSTRT IQCLK CDATA IQSTB CCLK CSTB VCC 6 5 4 3 2 1 44 43 42 41 40 VCC DATA6 DATA5 DATA4 DATA3 VCC GND CLK DATA2 DATA1 DATA0 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 GND RESET GND VCC VCC TDO TRST TMS TCK VCC TDI 39 38 37 36 35 34 33 32 31 30 29 GND DATA15 DATA14 DATA13 DATA12 GND DATA11 DATA10 DATA9 DATA8 DATA7 Pin Description NAME VCC GND DATA0-15 CLK RESET TYPE I I I +5V Power. Ground. Input Data Bus. Selectable between two's complement and offset binary. DATA0 is the LSB. Clock for input data bus. fS is the frequency of CLK, which is also the input sample rate. RESET initializes the internal state of the DDC. During RESET, all internal processing stops. RESET facilitates the synchronization of multiple chips for Auto Three-State operation. If the Force bits in Control Word 7 are inactive and the IEEE Test Access Port is in an Idle state, RESET causes the IQCLK, IQSTB, I and Q outputs to go to a high impedance state. All Control Registers are updated from their respective Control Buffer Registers on the third rising edge of CLK after the deassertion of RESET. If RESET is deasserted tRS nanoseconds prior to the rising edge of CLK, the internal reset will deassert synchronously. If tRS is violated, then the circuit contains a synchronizer which will cause reset to be deasserted internally one or more clocks later. An initial reset is required to guarantee proper operation of the DDC. Active low. I Q IQCLK IQSTB IQSTRT CDATA CCLK CSTB CS TCK TMS TDI TDO TRST O O O O I I I I I I I I O I The I output has three modes: I data; I data followed by Q data; real data. The Q output has two modes: Q data and the carry out of the Phase Adder. IQ Clock: Bit or word clock for the I and Q outputs. IQ Strobe: Beginning or end of word indicator for I and Q. IQ Start: Initiates output data sequence. Active low. Control Data: Port for control data input. Control Data Clock: Control data input bit clock. Control Data Strobe: Beginning of word indicator for control data. Chip Select: Enables control data loading of DDC. Active low. Test Clock: Bit Clock for IEEE 1149.1 Data. This signal should be either tied low or pulled high when the TAP is not used. Test Port Mode Select: This signal should be either left unconnected or pulled high when the TAP is not used. Test Data Input for IEEE Test Port: This signal should be either left unconnected or pulled high when the TAP is not used. Test Data Output for IEEE Test Port: This output will be in the high impedance state when the TAP is not used. Test Port Reset. Active Low. This signal should be tied low when the TAP is not used. DESCRIPTION 3-2 CS Q I DDC Functional Block Diagram MIXER SECTION HDF SECTION SCALING MULTIPLIER DATA RAM FIR SECTION MULTIPLIER/ ACCUMULATOR SHIFTER 17 HDF + 18 CLK R 17 18 SHIFT REGISTER I INPUT FORMAT 17 HDF SHIFT CLK HDF COEFFICIENT ROM DECIMATION COUNTER PRELOAD (DCP) DATA0-15 16 INPUT REGISTER SHIFTER HDF DATA RAM 22 CLK 4R CLKSER = IQCLK 3-3 COS 17 SIN 17 18 SIN/COS GENERATOR PHASE WORD 18 17 18 MULTIPLIER/ ACCUMULATOR FORMATTER (PARALLEL TO SERIAL CONVERTER AND BUFFER) + SHIFT REGISTER Q SCALE FACTOR SCALING MULTIPLIER GAIN MIN PHASE INCR DELTA PHASE INCR PHASE OFFSET MAX PHASE INCR MODE IQSTRT PHASE GENERATOR LOCAL OSCILLATOR WAIT FOR RAM FULL OUTPUT FORMAT TIME SLOT LENGTH NUMBER OF OUTPUT BITS OUTPUT SENSE I FOLLOWED BY Q TIME SLOT NUMBER IQCLK POLARITY IQCLK DUTY CYCLE IQCLK DURATION IQCLK THREE-STATE CTL IQSTRB POLARITY IQSTRB LOCATION IQSTRB THREE-STATE CTRL HSP50016 IQSTB 0 CS CSTB DECODER CDATA 2 CCLK 2 1 1 I POLARITY AND THREE-STATE CTRL Q POLARITY AND THREE-STATE CTRL IQ CLK RATE TEST ENABLE AND CONTROL SIGNALS IQCLK TCLK CONTROL PARAMETERS TMS IEEE 1149.1 TEST ACCESS PORT TDI TDO 7 CLK RESET D Q D Q 7 TRST CONTROL CONTROL BUFFERS REGISTERS Indicates parameters from control registers. FIGURE 1. FUNCTIONAL BLOCK DIAGRAM HSP50016 Phase Generator Block Diagram PHASE ACCUMULATOR PHASE OFFSET MUX > R E G 18 1 PHASE REGISTER R E G 33 18 PHASE WORD (TO THE SIN/COS GENERATOR) 0 > 33 + + MAXIMUM PHASE INCREMENT R E G 32 MUX SELECT 1 PHASE INCREMENT ACCUMULATOR PHASE INCREMENT REGISTER R E G PHASE ADDER CARRY OUT > INCREMENT > R E G 1 MUX MINIMUM PHASE 32 2 > MUX SELECT 0 DELTA PHASE INCREMENT > R E G 32 0 ADDER / SUBTRACTOR CARRY OUT INITIALIZE PHASE INCR. TO MIN INITIALIZE PHASE INCR. TO MAX MUX SELECT 0 CONTROL MUX SELECT 1 > MODE CONTROL Indicates parameters set in Control Registers. FIGURE 2. PHASE GENERATOR BLOCK DIAGRAM Functional Description The primary function of the DDC is to extract a narrow frequency band of interest from a wideband input, convert that band to baseband and output it in either a quadrature or real form. This narrow band extraction is accomplished by down converting and centering the band of interest at DC. The conversion is done by multiplying the input data with a quadrature sinusoid. A quadrature lowpass filter is applied to the multiplier outputs. Identical real lowpass filters are provided in the in-phase (I) and quadrature phase (Q) processing branches. Each filtering chain consists of a cascaded HDF and FIR filter, which extracts the band of interest. During filtering, the signal is decimated by a rate which is proportional to the output bandwidth. The bandwidth of the resulting signal is the double sided passband width of the lowpass filters. An Output Formatter manipulates the filter output to provide the data in a variety of serial data formats. 3-4 ADD/SUBTRACT HSP50016 Local Oscillator Signal data clocked into the DATA0-15 input of the DDC is multiplied by a quadrature sinusoid in the Mixer Section (see Figure 1). The data input to the DDC is a 16-bit real data stream which is sampled on the rising edges of CLK. It can be in two's complement or offset binary format. The input data is passed to a mixer, which is composed of two real multipliers. One of these multiplies the input data samples by the in-phase (cosine) component of the quadrature sinusoid, and the other multiplies the input data samples by the quadrature (sine) component. The in-phase and quadrature data paths are designated I and Q respectively. The sine and cosine are generated in the local oscillator as shown in Figure 1. The local oscillator is programmed to produce a quadrature sinusoid with programmable frequency and phase. The frequency can be constant (Continuous Wave - CW), linearly increasing (up chirp), linearly decreasing (down chirp), or linear up/down chirp. The initial phase of the waveform is set by the phase offset. The phase, frequency and chirp limits of the quadrature sinusoid are controlled by the Phase Generator (Figure 2). The output of the Phase Generator is an 18-bit phase word that represents the current phase angle of the complex sinusoid. The Phase Generator automatically increments the phase angle by a preprogrammed amount on every rising edge of CLK. Stepping the output phase from 0 through full scale (218 - 1) steps the phase angle of the quadrature sinusoid from 0 to (-2+2-17) radians. NOTE: The phase is stepped in a clockwise (decreasing) direction to support down conversion. The frequency of the complex sinusoid is determined by the number of clocks needed for the phase to step though its full range of 2 radians. The required phase increment for a given local oscillator frequency is calculated by: Phase Increment = INT [ ( f C f S ) 2 ]H - 33 ; 0 < f C < f S /2 f C = ( Phase Incr ) f S 2 33 minimum phase increment is the phase step taken on every clock. When the SIN/COS Generator is producing a chirped sinusoid, the minimum phase increment is the smallest phase step taken. Maximum phase increment is only used during Chirped Modes; it is the largest allowable phase increment. During Chirp Modes, the delta phase increment is the difference between successive phase increments. The four phase parameters are stored in their respective registers in the Phase Generator. The Phase Register stores the current phase angle. On the first clock following the deassertion of RESET, the 18 MSBs of the Phase Register are loaded from the Phase Offset Register. On every rising edge of CLK thereafter, the output of the Phase Increment Register is subtracted from the 32 LSBs of the current phase. The 33-bit difference is stored back in the Phase Register on the next CLK. The 18 most significant bits of the Phase Register form the phase word, which is the input to the SIN/COS Generator. Figure 3 gives a graphic representation of the phase parameters for the CW case. To understand their interrelationships, the phase should be visualized as the angle of a rotating vector. When the local oscillator in the DDC is programmed to generate a CW waveform, the multiplexers are configured so that the Minimum Phase Increment is stored in the Phase Increment Register; this value is subtracted from the output of the Phase Register on every CLK and the difference becomes the new Phase Register value. The Delta Phase Increment and Maximum Phase Increment are ignored when generating a CW. STARTING PHASE +90o INCR (0) (1) (2) 180o OFFSET INCR INCR INCR 0o (EQ. 1) where: fC is the desired local oscillator frequency fS is the input sampling frequency Phase Increment is the Control Word Value (in Hex) There are five parameters which control the Phase Generator: Phase offset, minimum phase increment, maximum phase increment, delta phase increment and Mode Control. These values are programmed via Control Words 2, 3, and 4. Mode Control is used to select the function of the other parameters. The phase offset is the initial setting of the phase word going to the SIN/COS Generator. Subsequent phases of the sinusoid are calculated relative to this offset. The minimum phase increment has two mode dependent functions: when the SIN/COS Generator is forming a CW waveform, the (3) (4) (5) INCR -90o FIGURE 3. PHASE WORD PARAMETERS FOR CW CASE In Up Chirp Mode the local oscillator generates a signal with a linearly increasing frequency (Figure 4A). The Phase Increment Register is initially loaded with the minimum Phase Increment value; on every clock, the contents of the Phase Increment Register is subtracted from the current output of the Phase Register. Simultaneously, the Delta 3-5 HSP50016 Phase Increment Register is added to the 24 LSBs of the output of the Phase Increment Register. On the next CLK, that sum is stored back in the Phase Increment Register, the new phase is stored in the Phase Register and the process is repeated. The phase increment is allowed to grow until the next phase increment would equal or exceed the maximum phase increment value. When this happens, the Phase Increment Register is reset to the minimum phase increment and the cycle starts over again. NOTE: The phase increment is never equal to the maximum phase increment, since the Phase Increment Register is reloaded if the next phase increment value would be greater than the maximum phase increment. From the time the Phase Generator starts at the minimum phase increment until it reaches the maximum phase increment, the phase word on clock n is given by: In Down Chirp Mode the local oscillator generates a signal with a linearly decreasing frequency (Figure 5A). The maximum phase increment is loaded into the Phase Increment Register and the phase offset value goes into the Phase Register. The delta phase increment is subtracted from the 24 LSBs of the phase increment to form a new phase increment at each clock. The phase increment is allowed to diminish until it reaches the minimum phase increment value, then it is reset to the maximum phase increment value and the cycle is repeated. Note that the value of the phase increment can be equal to, but never less than the minimum phase increment, since the Phase Increment Register is reloaded if the next phase increment value would be less than the minimum phase increment. This feature protects the DDC from exceeding the Nyquist frequency. In this case, from the time the Phase Generator starts at the maximum phase increment until it reaches the minimum phase increment, the phase word on clock n is given by: Phase Offset - [Minimum Phase Increment (EQ. 2) + n (Delta Phase Increment) ] Phase Offset -[Minimum Phase Increment (EQ. 3) - n (Delta Phase Increment)] An example of the outputs of the Phase Increment Register, Phase Register, and the I output of the SIN/COS Generator are shown in Figure 4B. See Figure 5B for a graphical representation of this process. PHASE INCREMENT STARTING PHASE MAXIMUM +90o MINIMUM TIME INCR INCR + 2 (8) (0) (1) (2) 180o (7) (3) (6) 0o OFFSET INCR + PHASE WORD INCR + INCR (5) INCR + 2 PHASE OFFSET TIME (4) INCR + 3 INCR + 4 IF -90o COSINE OUTPUT OF SIN/COS GENERATOR INCR + 5 > MAX INCR THEN START NEW RAMP TIME FIGURE 4A. PHASE WORD DURING UP CHIRP FIGURE 4B. UP CHIRP 3-6 HSP50016 PHASE INCREMENT MAXIMUM TIME MINIMUM STARTING PHASE +90o MAX INCR -4 (5) (0) OFFSET PHASE WORD PHASE OFFSET TIME 0o MAX INCR 180o -3 (4) (3) (1) (2) MAX INCR COSINE OUTPUT OF SIN/COS GENERATOR MAX INCR -2 MAX INCR - -90o TIME FIGURE 5A. PHASE WORD DURING DOWN CHIRP FIGURE 5B. DOWN CHIRP PHASE INCREMENT MAXIMUM TIME MINIMUM PHASE WORD PHASE OFFSET TIME COSINE OUTPUT OF SIN/COS GENERATOR TIME FIGURE 6. UP/DOWN CHIRP In Up/down Chirp Mode, the phase accumulator is set to the phase offset value and the minimum phase increment is loaded into the Phase Increment Register. The delta phase increment is added to the 24 LSBs of the Phase Increment Register to form a new phase increment at each clock. The phase increment is allowed to grow until it nears the maximum phase increment value (as defined in the up chirp description). The delta phase increment value is then subtracted from the least significant bits of the Phase Increment Register to form a new phase increment at each clock. The phase increment is allowed to diminish until it 3-7 reaches the minimum phase increment value (as defined in the down chirp description). The Phase Increment Register is then reloaded with the minimum phase increment, and the up/down cycle begins again. See Figure 6 for a graphical representation of this process. The minimum and maximum phase increments have allowable values from 0 to 232-1. This corresponds to the phase increment: 0 < Phase Increment < ( 1 - 2 - 32 ) radians (EQ. 4) HSP50016 The Delta Phase Increment parameter can take on values from 0 to 224 - 1 which corresponds to the Delta Phase Increment: 0 < DeltaPhase Increment < ( 2 -8 -2 - 32 ) radians (EQ. 5) the input data to the HDF for the maximum dynamic range while avoiding overflow errors. The shift factor is programmed into the Shift field of Control Word 4. The value in this field is calculated by the equation: Shift = 75 - Ceiling ( 5 log 2 ( R ) ) (EQ. 7) The output of the phase accumulator forms the input to the SIN/COS Generator which in turn produces a quadrature vector which rotates clockwise: the outputs are cos(n) and -sin(n). The outputs of the SIN/COS Generator are two's complement values which are scaled to prevent overflow in subsequent operations in the DDC under normal operation. The scale factor has a negligible effect on the end to end DDC gain. The frequency resolution of the DDC = (frequency of CLK)/ (Number of Phase Register bits). At the maximum clock rate, this results in a frequency selectivity of 75MHz/233 = 0.009Hz. The 18-bit phase word yields a phase noise figure of greater than 102dB. where R is the HDF decimation factor and Ceiling(X) denotes the ceiling function of X; i.e., the result is X if X is an integer, otherwise the result is the next higher integer. During RESET, the HDF is initialized and will not output any information until it is filled with new data. NOTE: The output rate of the HDF is CLK divided by the HDF decimation factor (CLK/R). The HDF decimation counter preload (DCP) is programmed in Control Word 5, bits 21-35 and has the value: DCP = R -I, where R is the HDF decimation factor. 0 Mixer The Mixer performs quadrature modulation by multiplying the output of the SIN/COS Generator by the input data. The outputs of the I and Q multipliers are symmetrically rounded to 17 bits to preserve the 102dB spurious free dynamic range (SFDR). The result of the quadrature modulation process is passed to the High Decimating Filter (HDF) Section. -20 -40 GAIN (dB) -60 -80 High Decimation Filter The High Decimation Filter (HDF) Section is comprised of two real HDF filters, one processing the I data branch and one processing the Q data branch. Each branch has the lowpass response shown in Figure 7. The normalized HDF frequency impulse response is given by the equation: Sin ( F S ) 5 I 5 --H ( f ) = ------------------------------R Sin ( F S /R ) (EQ. 6) -100 -120 fS 8R fS 4R 3fS 8R fS 2R 5fS 8R 3fS 4R 7fS 8R fS R FREQUENCY (Hz) FIGURE 7A. FREQUENCY RESPONSE OF HIGH DECIMATION FILTER FROM DC TO FIRST NULL (FOR R = 16) Gain (dB) = 20log [H(f)] where FS is the input sampling rate; R is the decimation (rate change) factor. 0 Figure 7A shows this equation plotted from DC to the first null, while Figure 7B shows the equation plotted from DC response to fS. NOTE: The HDF is a true FIR filter; i.e., the phase is linear. The data path through the HDF was designed to ensure a true 16-bit noise floor (approximately 98dB) at the output of the DDC. The structure of the HDF filter used in the DDC is a five stage decimation filter. The width of each successive stage decreases such that the LSBs are lost due to truncation [1]. As a result, the data must be processed in the MSBs of the filter so that the noise due to truncation is below the required noise floor. Thus, the input data of the HDF must be shifted so that its output data fills the HDF output word. The shift is a function of the desired HDF decimation rate R and the number of HDF filter stages (which is fixed at 5). The shift is performed by the Data Shifter, which positions 3-8 GAIN (dB) -20 -40 -60 -80 -100 -120 fS 2fS R R 4fS R 6fS fS 10fS 12fS R 14fS R fS R 2 R FREQUENCY (Hz) FIGURE 7B. DDC HC FREQUENCY RESPONSE (FOR R = 16) Gain (dB) = 20log[H(f)] HSP50016 Scaling Multipliers The output of each HDF is passed to a Scaling Multiplier. The Scaling Multipliers are used to compensate for the HDF gain, which is between 1 (inclusive) and 0.5 (non-inclusive), or (0.5, 1.0). The gain through the HDF is dependent on the decimation factor: when the decimation is an even power of two, the HDF gain is equal to 1; otherwise, the gain must be compensated for in the Scaling Multiplier. The HDF gain is given by the equation: 5 HDF Gain = R /2 CEILING ( 5 log 2 ( R ) ) The binary formats of the inputs and outputs of the scaling multiplier are as follows: Input from HDF: Scale factor: Output: a0(-20). a1(2-1) a2(2-2)... a17(2-17) a0(20). a1(2-1) a2(2-2)... a15(2-15) a0(-20). a1(2-1) a2(2-2)... a16(2-16) FIR Filter The Scaling Multiplier output is passed to the FIR Filter, which performs aliasing attenuation, passband roll off compensation and transition band shaping. The FIR Filter Section is functionally two identical 121 tap lowpass FIR filters, one each for the I and Q channel. The two filters are each implemented as sum of products, each with a single multiplier, with the coefficients stored in ROM. The filters' passbands are precompensated to be the inverse of the response of the HDF. The frequency responses of the HDF, FIR, and Composite HDF/FIR filters are shown in Figure 8. The composite passband of the HDF and FIR filter frequency response is shown in Figure 9. The FIR coefficients are scaled so that the maximum gain of the composite filter is less than or equal to 0dB. The composite passband ripple is less than 0.04dB. (EQ. 8) where R is the HDF decimation factor. The compensating Scale Factor, which is input to both Scaling Multipliers, is given by the equation: 5 Scale Factor = 2 CEILING ( 5 log 2 ( R ) ) R (EQ. 9) where R is the HDF decimation factor. NOTE: The Scale Factor falls in the interval [1, 2). The output of the scaling multiplier is symmetrically rounded to 17 bits. MAGNITUDE (dB) HDF 0 -50 -100 -150 fS fS 2 3fS 4 -20 MAGNITUDE (dB) fS 0 HDF (R = 16) MAGNITUDE (dB) 4 FIR 0 -50 -100 -150 fS 4 fS 2 3fS 4 fS -40 -60 -80 COMPOSITE HDF/FIR FIR MAGNITUDE (dB) COMPOSITE 0 -50 -100 -150 fS 4 fS 2 SAMPLE TIMES 3fS 4 fS -120 2 fS 46 fS -100 8 10 12 14 16 18 20 22 24 26 28 30 32 fS fS 3fS fS 32R 16R SAMPLE TIMES 32R 8R 128R 64R FIGURE 8A. DDC HDF, FIR, AND COMPOSITE FILTER RESPONSE (FOR R = 16) FIGURE 8B. DDC FILTER RESPONSES (FOR R = 16) 3-9 HSP50016 0.5 0.4 0.3 MAGNITUDE (dB) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 fS 64R fS 32R FREQUENCY (Hz) 3fS 64R fS 16R HDF FIR COMPOSITE HDF/FIR FIGURE 9. FIR COMPENSATION FOR HDF ROLL OFF (FOR R = 16) The coefficients of the filter are quantized to 22 bits to preserve greater than 106dB of stopband attenuation. The sum of products of each filter output calculation is a 38-bit number with 37 fractional bits. When a quadrature output is selected, the outputs of the FIR filters are decimated by a factor of four. When real output is selected, only the I output is active. The output is decimated by two in this case. When Filter Only Mode is selected, only the I filter path is active and its output is decimated by four. The composite filter bandwidths are a function of the HDF decimation rate and the FIR Filter shape. The double sided bandwidths are specified by Equations 10 and 11. - 3dB BW DS = 0.1375F S R 16 < R < 16384 (EQ. 10) TABLE 1. FIR OUTPUT RATE AND DECIMATION OUTPUT MODE Real Complex Filter Only R - HDF Decimation Factor FIR OUTPUT RATE CLK/2R CLK/4R CLK/4R FIR DECIMATION 2 4 4 Output Formatter The circuit has two serial data outputs, I and Q. The timing of the output bits is referenced to IQCLK and IQSTB. There are several modes of operation for the data and control line interface, all of which were designed to be compatible with common microprocessors. These interface modes are selected by loading the appropriate control words (see Tables 3 through 10, with Table 9 containing most interface parameters). Quadrature data output can occur in one of two ways: simultaneously or sequentially. The simultaneous method clocks out the I and Q data on their respective serial output pins. The I followed by Q method clocks I and Q out sequentially on the I output pin: the entire I word is serially clocked out first, then the entire Q word. In real data Output Mode, the Formatter converts the quadrature data to real and clocks it out serially on the I output pin. In all modes, the I and Q outputs return to the zero state after the last bit is transmitted. When the "I followed by Q" signal (CW6, bit 35) is low, I data will appear on the I output and Q data will appear on the Q output. When the "I followed by Q" signal (CW6, bit 35) is asserted, the Q output is inactive and I data, followed by Q data appear on the I output. When in this state, and both the "Test Enable" signal (CW1, Bit 3), and "Q Strobe on Rollover" signal (CW7, Bit 10) signal are asserted, the Phase - 102dB BW DS = 0.2002F S R 16 < R < 16384 (EQ. 11) where FS = CLK; R = HDF Decimation Factor. The single sided bandwidths are specified in Equations 12 and 13. - 3dB BW SS = 0.06875F S R - 102dB BW SS = 0.100097F S R (EQ. 12) (EQ. 13) where FS = CLK; R = HDF Decimation Factor. NOTE: The output data rate of the FIR is the HDF output rate divided by either 2 or 4, depending on mode. Recall the HDF output rate is CLK/R. (See Table 1.) 3-10 HSP50016 Generator Carry Out will appear on the output. Control Word 5 contains fields to set the number of output bits transmitted to the arithmetic representation and interface control of the serial output data. Control Word 4, Bits 31-32, allow selection of baseband centered quadrature on baseband offset quadrature complex outputs. Control Word 4, Bit 0, allows selection of spectral inversion. In addition, the output drivers for I, Q, IQCLK and IQSTB can be individually enabled or placed in a high impedance state using Control Word 6, Bits 20-28. These options are explained below. When the "Output Spectrum" signal (CW4, bits 31-32) is set to "01", then the real output data appears on the I output and the Q output in the I/Q separate mode. When in I Mode followed by Q Mode, the Q slot is also real data since the real mode outputs at twice the rate of the complex mode (CW4, bits 31-32 = 00). When set for fixed point output, the output data can be in two's complement, offset binary or signed magnitude form. Data is converted to offset binary by complementing the most significant bit of a two's complement number. The length of the output data word can be 16, 24, 32 or 38-bits. The first three options are symmetrically rounded to the LSB of the output data; the fourth option represents the full 38-bit width of the accumulator and so represents exact arithmetic. The output has a saturation option to prevent possible overflow due to a step input at power up. When Overflow Protection is enabled, the output is forced to be either the most positive or most negative number. Saturation is available in all four fixed point output options, and is set via Control Word 7, Bit 0. Data can also be output in single precision floating point format (see Table 2). For all output data formats, the internal calculations are performed in exact two's complement integer arithmetic and the resulting data is converted in the Output Formatter. TABLE 2. FLOATING POINT FORMAT SIGN -20 EXPONENT 27 to 20 MANTISSA Implied 1 0.2-1 to 2-23 I STOP BIT Q B. I FOLLOWED BY Q OUTPUT MODE and trailing zero bits occur before bit 0 and after bit N, respectively. CLK IQCLK Rate = ------------------------------------------------- - 1 IQCLK Frequency (EQ. 14) I STOP BIT Q STOP BIT N N-1 1 0 START BIT N N-1 1 0 START BIT N = 16, 24, 32 OR 38 A. SIMULTANEOUS OUTPUT MODE QN QN-1 Q1 Q0 START STOP BIT BIT QN QN-1 Q1 Q0 START BIT FIGURE 10. DATA OUTPUT MODES IQCLK is used to delineate the bit or word timing of the I and Q outputs. There are several options on the configuration of IQCLK, which are controlled with Control Word 6 (see Table 8). The frequency of IQCLK is programmed to be a fraction of the CLK frequency, from (CLK rate)/2 to (CLK rate)/8192 (see Equation 14). If IQCLK Rate = 0, then IQCLK remains in its inactive state and the output bits change on the rising edges of CLK. IQCLK can be programmed to be active continuously, or only during I or Q data output via the IQCLK duration bit. Using the IQCLK Duty Cycle bit, IQCLK is selectable as either 50% duty cycle or to be high for one period of CLK. In addition, the Formatter can be set so that the data bits are clocked on either the positive or negative edges of IQCLK with the IQCLK Polarity bit. Figure 11 shows the various modes of operation with IQCLK Polarity programmed for active high operation. Control Word 6 also configures IQSTB, as shown in Figure 12. When programmed for Active Prior to Data Word, IQSTB is high for one period of IQCLK and terminates simultaneously with the beginning of the first data bit; otherwise it goes active with the beginning of the first bit and inactive with the end of the last bit. IQSTB can be programmed to be either active high or low. The I and Q pins can be programmed for either simultaneous or I followed by Q output. In simultaneous mode, the I and Q data appear on the I and Q pins, respectively. Each data sample is preceded by a leading zero bit, followed by the output data, followed by a trailing zero bit. In I followed by Q Mode, the output data appears on the I pin, and consists of a leading zero bit, then the I data, a trailing zero, a leading zero, the Q data, and finally a trailing zero bit. In Figures 10 through 12, the leading 3-11 HSP50016 CCLK CLK IQCLK CDATA I OR Q BIT 0 BIT 1 BIT N-1 BIT N CSTB CS CLK IQCLK I OR Q BIT 0 BIT 1 BIT N-1 BIT N BIT39 BIT 36 BIT35 BIT 0 A. IQCLK DUTY CYCLE: ACTIVE TIME = CLK PERIOD (IQCLK POLARITY = 0) FIGURE 14. CONTROL WORD TIMING DIAGRAM B. IQCLK DUTY CYCLE: 50% IQCLK I OR Q BIT 0 BIT 1 BIT N-1 BIT N C. IQCLK DURATION: CONTINUOUS IQCLK I OR Q BIT 0 BIT 1 BIT N-1 BIT N D. IQCLK DURATION: ACTIVE DURING I OR Q ONLY Data can be read out of the DDC on request through the use of the IQSTRT pin. After passing through the Output Formatter, the I and Q data are stored in output buffers, which are updated at the end of the FIR Filter processing cycle. The IQSTRT and IQSTB lines form a two line handshake as shown in Figure 13. IQSTRT initiates the request. If the buffer has data in it, the DDC will begin an output data sequence on the next edge of IQCLK. The DDC will then put out one bit per IQCLK until the output cycle is complete. In I followed by Q Mode, one IQSTRT will initiate an I output word followed by a Q output word. In real data Output Mode, one IQSTRT will initiate two samples of real data on the I pin. To avoid the generation of multiple read cycles, IQSTRT must go inactive within 10 cycles of IQCLK after the initiation of IQSTB. The DDC will not update the output buffer again until the current output cycle has completed. When IQSTRT is used in this handshake mode, it must consist of pulses that satisfy the set up and hold requirements listed in the AC Timing Specifications and the pulses must occur at a rate of at least CLK/(HDF Decimation Factor x 4 -1). This mode of operation requires the Time Slot Number in Control Word 6 to be 0. NOTE: When handshake mode is not used, IQSTRT should be at a logic low. FIGURE 11. TIMING FOR CLK, IQCLK, IQSTB, I AND Q IQCLK BIT 0 BIT 1 BIT N-1 BIT N I OR Q I/QSTB A. IQSTB ACTIVE PRIOR TO DATA WORD IQCLK I OR Q IQSTB B. IQSTB ACTIVE DURING DATA WORD BIT 0 BIT 1 BIT N-1 BIT N FIGURE 12. IQSTB TIMING IQCLK LEADING 0 TRAILING 0 I or Q IQSTRT BIT 0 BIT N Auto Three-State Mode for IQCLK, IQSTB, I and Q allows multiple chips to operate using common data and output control lines. Each chip is assigned a Time Slot Number on the bus to use for outputting its data. All outputs programmed for Auto Three-State Mode are active during their time slot and are in a high impedance state at all other times. A time slot starts one CLK period prior to the beginning of the first bit of I or Q and ends (Time Slot Length) CLK periods afterwards. Assignment of a time slot is with reference to the deassertion of RESET. The minimum possible Time Slot Length for a given application is: Length MIN = [ ( Numberof Output Bits + 2 ) x Mode ] + 1 ; or (EQ. 15) IQSTB where Mode = 2 if the DDC is in either Real Output or I followed By Q Mode; else Mode = 1. FIGURE 13. REQUESTED DATA OUTPUT TIMING 3-12 HSP50016 Note that Equation 15 is useful in all modes for calculating the number of IQCLKs necessary to complete one output data cycle. For a given decimation rate and output word length, the maximum value in the IQCLK Rate field is: (R) x 4 IQCLKRate MAX = Floor ------------------------------ - 1; Length MIN (EQ. 16) Control Word Input The DDC has eight 40-bit control words which are loaded through the four pin control interface. The format and timing of this interface is compatible with the serial interface timing of most common DSP microprocessors (see Figure 14). The words are shifted MSB first, where bit 39 of the control word is the MSB. Bits 39 through 37 are the control word address, i.e., the target control buffer. CS must go low before bit 35 is clocked in. All 40 bits of the control word must be loaded. The formats of the control words are shown in Tables 3 through 10. The control words are double buffered: each control word is initially loaded into one of eight control buffers for subsequent down loading into the corresponding Control Register. The internal circuitry of the DDC uses the Control Registers to regulate its operation. Control buffers can be downloaded in one of two ways. Loading a Buffer Register with bit 36 = 1 causes all Control Registers to be updated from their respective control buffers when the current word is finished loading. If bit 36 = 0, then only that control buffer is updated and the operation of the DDC is not affected. All Control Registers are updated from their respective buffers on the third rising edge of CLK following the deassertion of RESET. NOTE: Control Word 0 is unique in that it is only used to update the seven Control Registers, and it is recognized by the DDC regardless of the state of CS. In systems with multiple DDCs, this allows the user to update the configuration of all chips simultaneously without using RESET. To ensure that the control information is properly loaded, the frequency of CLK must be greater than the frequency of CCLK. In addition, RESET must remain inactive during the loading of a control word. where Floor(X) represents the integer part of X, R is the HDF decimation factor, 4 is the FIR decimation factor. Example Clock Calculations Clarification of the use of Equations 14-16, the calculation of the HDF and FIR clocks and the calculation of the IQCLK is best done by example: The sample clock, CLK, is 10MHz . . . . . . . . CLK = 10MHz The HDF Decimation Factor, R, is 100 (which makes the decimation counter preload = 99). . . . . . . . . . . . . . . R = 100 The Output Mode is I followed by Q . . . . . . . . . . . . Mode = 2 Complex output . . . . . . . . . . . . . . . . . . . FIR Decimation = 4 The desired number of output bits is 32. 1. We begin by identifying the HDF Input Rate: HDF Input Rate = CLK = 10MHz . . . . . . . CLK = 10MHz 2. Next we calculate the HDF Output Rate: HDF Output Rate = CLK/R = 10MHz/(100) = 100kHz . . . . . . . . . . . . . . . . . . . . . . .HDF Output Rate = 100kHz 3. Next we calculate the FIR output Rate: FIR Output Rate = CLK/4R = 25kHz. . . . . . . . . . . . . . . . . . . . . . . . . FIR Output Rate = 25kHz 4. Next we calculate the minimum time slot length: Equation 15: LengthMIN = [(Number of Output Bits + 2) x Mode] +1 where the number of output bits = 32 and the Mode is 2 because of the I followed by Q output selection. LengthMIN = [(32 + 2) x 2] +1 = 69 IQCLKs . . . . . . . . . . . . . . . . . . . . . . . . . LengthMIN = 69 IQCLKs 5. Next we calculate the IQCLK frequency: IQCLK frequency = [( FS )(LengthMIN)/(R)(4)] - 1 IQCLK frequency = [(10MHz)(69)/(100)(4)] - 1 = 1.725MHz The IQCLK frequency can be no slower than 1.725MHz if all of the bits are to be output of the DDC in a time slot. . . . . . . . . . . . . . Slowest Serial Output Rate = 1.725MHz 6. The Programmed value for the maximum IQCLK Rate, from Equation 16, is: IQCLKRATEMAX = Floor[(R) x 4/ LengthMIN] -1 IQCLKRATEMAX = Floor[(100 x 4)/69] - 1 = 4 The IQCLKRATE can be not greater than 4 if all of the bits are to be output of the DDC in a time slot. . . . . . . . . . . . Control Word Value for IQCLK Ratemax = [00004]H; 0 0000 0000 0100LSB 7. Let's sanity check with Equation 14. IQCLK Rate = [(CLK/IQCLKfreq)-1] = [10E6/1.725E6] -1 = 4. This checks! 3-13 HSP50016 TABLE 3. DESTINATION ADDRESS = 0 BIT POSITION 39-37 36 FUNCTION Address Update 000 = Control Word 0 0 = Update Only This Control Register 1 = Update All Control Registers All Zeroes DESCRIPTION 35-32 Reserved TABLE 4. PHASE GENERATOR/TEST ENABLE/OUTPUT REGISTER DESTINATION ADDRESS = 1 BIT POSITION 39-37 36 FUNCTION Address Update 001 = Control Word 1 0 = Update Only This Control Register 1 = Update All Control Registers DESCRIPTION 35-4 Minimum Phase Increment Bits 35-4 = 231...20. Range: 0 < Minimum Phase Increment < (1-2-32) radians. In the CW mode this is the phase increment of the NCO which is added to the NCO intitial phase offset state. The desired Sin/Cos generator (local oscillator) frequency is set by the equation: fc = (phase increment)fs2-33; where fc is the desired local oscillator frequency, fs is the input sampling frequency, and phase increment is the control word value in hexidecimal. To calculate the value to be programmed into this field, use this equation: phase increment = INT[fc / fs)233]hex Some examples of phase increments and local oscillator frequencies: 00000000h: fc = zero frequency 00000001h: fc = fs /233 - lowest frequency (75MHz x 2-33 = 8.73mHz) 10000000h: fc = fs /32 20000000h: fc = fs /16 40000000h: fc = fs /8 80000000h: fc = fs /4 ffffffffh: fc = (0.49999)fs - highest frequency (75MHz x 2-33 = 37.49MHz) In the CHIRP modes, this is the smallest allowable phase increment. In the Filter Only mode, this parameter should be set to 0. 3 Test Enable 0 = Test Features Disabled 1 = Test Features Enabled 2-0 Phase Generator Mode 000 = Filter Only 001 = Normal Mode (CW) 010 = Reserved 011 = Up Chirp 100 = Reserved 101 = Down Chirp 110 = Reserved 111 = Up/Down Chirp Note that the lsb sets the gain through the DDC as follows: 0 = Gain is1 1 = Gain is 2 3-14 HSP50016 TABLE 5. PHASE GENERATOR REGISTER DESTINATION ADDRESS = 2 BIT POSITION 39-37 36 35-32 31-0 FUNCTION Address Update Reserved Maximum Phase Increment 010 = Control Word 2 0 = Update Only This Control Register 1 = Update All Control Registers All Zeroes Bits 31-0 = 231... 20. Range: is 0 < Maximum Phase Increment < (1-2-32) radians. This parameter is only used in the CHIRP modes, and this is the largest allowable phase increment. Set to 0 in the Filter Only and CW modes. DESCRIPTION TABLE 6. PHASE GENERATOR/OUTPUT TIME SLOT REGISTER DESTINATION ADDRESS = 3 BIT POSITION 39-37 36 FUNCTION Address Update 011 = Control Word 3 0 = Update Only This Control Register 1 = Update All Control Registers All Zeroes DESCRIPTION 35-32 31-18 Reserved Time Slot Length Time Slot Length in IQCLK Periods; Bits 31-18 = 213... 20. Range is (19,25, 33, 37, 39, 49, 65 and 77) The equation for calculating the value for this field is: TSL = [[(Number of Output Bits + 2)Mode ] + 1]Hex; where mode is 2 if the DDC is in either the real or I followed by Q mode. Mode is 1 for all other DDC operational modes. Allowable Minimum Time Slot Lengths: (18)1 + 1 = 19 (13 hexidecimal) (18)2 + 1 = 37 (25 hexidecimal); Real Output or I followed by Q (24)1 + 1 = 25 (19 hexidecimal) (24)2 + 1 = 49 (31 hexidecimal); Real Output or I followed by Q (32)1 + 1 = 33 (21 hexidecimal) (32)2 + 1 = 65 (41 hexidecimal); Real Output or I followed by Q (38)1 + 1 = 39 (27 hexidecimal) (38)2 + 1 = 77 (4d hexidecimal); Real Output or I followed by Q 17-0 Phase Offset Starting Phase Angle of Phase Accumulator; Range = 0 to 2. Bits 17-0 = 232... 215. Some example phase offset hexidecimal values : 0000 - 0 1000 - /2 2000 - 3000 - 3/2 3fff - 2 3-15 HSP50016 TABLE 7. PHASE GENERATION/HDF.OUTPUT REGISTER DESTINATION ADDRESS = 4 BIT POSITION 39-37 36 FUNCTION Address Update 100 = Control Word 4 0 = Update Only This Control Register 1 = Update All Control Registers All Zeroes 00 = No Up Conversion,Complex Output 01 = Up Convert by f"/4, Real Output 10 = Up Convert by f"/2,Complex Output 11 = Reserved Mode DESCRIPTION 35-33 32-31 Reserved Output Spectrum 30-7 Delta Phase Increment 24-Bit Delta Phase Increment. Bits 30-7 = 223... 20. Range: 0 < Delta Phase Increment < (2-8-2-32) 16-Bit HDF Gain Compensation Number - the shift portion. HDF Input Data Shift (Towards LSB). Bits 6-1 = 25...20. Range: 0 Shift Factor 55 decimal; Range: [0 Shift Factor 37]hex Calculate the value for this field using this equation: HDF Data Shift = [75 - Ceiing(5 log2(R))]hex Note: log2(x) = (3.32)log(x) 0 = Normal Output 1 = Spectrally Reversed Output 6-1 HDF Data Shift (Shift Factor) 0 Spectral Reverse TABLE 8. HDF/OUTPUT REGISTER DESTINATION ADDRESS = 5 BIT POSITION 39-37 36 FUNCTION Address Update 101 = Control Word 5 0 = Update Only This Control Register 1 = Update All Control Registers DESCRIPTION 35-21 HDF Decimation Counter Preload (HDF DCP) HDF Decimation Counter Preload. Range: 15 < HDF Decimation Counter Preload < 32,767 Calculate the value for this feild using this equation: HDF DCP = R - 1; where R is the HDF decimation (rate change) factor. Common HDF decimation (rate change) factors and associated hexidecimal HDF DCP values: 000f: R = 16 00ff: R = 128 01ff: R = 512 03ff: R = 1,024 07ff: R = 2,048 0fff: R = 4,096 1fff: R = 8,192 3fff: R = 16,384 7fff: R = 32,768 3-16 HSP50016 TABLE 8. HDF/OUTPUT REGISTER (Continued) DESTINATION ADDRESS = 5 BIT POSITION 20-5 FUNCTION Scaling Multiplier Gain (Scale Factor) DESCRIPTION 16-Bit HDF Gain Compensation Number - the multiplier portion. Range: 1 Scale Factor < 2, Field Format = 20.2-1...2-15. Calculate the value for this field using this equation: Scale Factor = 2CEILING(5log2(R))/(R)5; where R is the HDF decimation (rate change) factor and CEILING(x) is equal to x for integer values, otherwise is equal to the next higher integer. Common HDF decimation factors (R), decimation counter preload (DCP) and Scale Factors (SF) values: R 16 128 512 1,024 2,048 4,096 8,192 16,384 32,768 DCP(dec) 15 127 511 1,023 2,047 4,095 8,191 16,382 32,768 DCP(hex) 000f 007f 01ff 03ff 07ff 0fff 1fff 3fff 7fff SF(dec) 1.000 1.000 1.00 1.000 1.000 1.000 1.00 1.00 1.000 SF(hex) 8000 8000 8000 8000 8000 8000 8000 8000 8000 Note that the Scale Factor is 1 (8000hex) for power of 2 decimation factors. The compensation for the HDF gain is performed with a shifter and a multiplier. Thus to program the HDF Gain compensation, there is an associated Shift Factor and the Scale Factor. As the Decimation Factor increases, the multiplier moves away from the value 1 and approaches the value 2. When the calculated value for the multiplier equals or exceeds 2, the shifter is incremented and the multiplier returns to 1 and increases towards 2 again as the Decimation Factor increases. As an example, the table below details the values of Scale Factor for values of R from 16 to 32: R 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 4-3 Output Format DCP(dec) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 DCP(hex) 000f 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 001a 001b 001c 001d 001e 001f SF(dec) 1.000000000 1.477013647 1.109857915 1.693916116 1.310720000 1.026983417 1.627707993 1.303318981 1.053497942 1.717986918 1.412060017 1.169233029 1.949663831 1.635911864 1.380840823 1.172037271 1.000000000 SF(hex) 8000 BD0E 8E0F D8D2 A7C5 8374 D058 A6D3 86D9 DBE6 B4BE 95A9 F98E D165 B0BF 9605 8000 00 = Two's Complement 01 = Offset Binary 10 = Sign Magnitude 11 = Single Precision Floating Point Format 3-17 HSP50016 TABLE 8. HDF/OUTPUT REGISTER (Continued) DESTINATION ADDRESS = 5 BIT POSITION 2-1 FUNCTION Number Of Output Bits 00 = 16 Bits 01 = 24 Bits 10 = 32 Bits 11 = 38 Bits 0 = LSB First 1 = MSB First DESCRIPTION 0 Output Sense TABLE 9. INPUT AND OUTPUT FORMAT REGISTER DESTINATION ADDRESS = 6 BIT POSITION 39-37 36 FUNCTION Address Update 110 = Control Word 6 0 = Update Only This Control Register 1 = Update All Control Registers 0 = I and Q Output Separately 1 = I and Q Data Output on I Pin DESCRIPTION 35 I followed by Q 34-29 Time Slot Number Bits 34-29 = 25...20. Range: 0 < Time Slot Number < 63. This implies that 64 different channels may be mutliplexed, assigning one time slot per channel. 0 = Output Data Stable On Rising Edge Of IQCLK; IQCLK High between I or Q Bit Periods when IQCLK Duration = 0. 1 = Output Data Stable on Falling Edge of IQCLK; IQCLK Low between I or Q Bit Periods when IQCLK Duration = 0. 0 = IQCLK Active Time = CLK Period. 1 = 50% Duty Cycle 0 = Active During I or Q Output Periods Only 1 = Active Continuously 00 = Three-State IQCLK 01 = Enable IQCLK 1x = Auto-Three-State Enable IQCLK (during time slot) 0 = Active High 1 = Active Low 0 = IQSTB Prior to the Beginning of the Data Word. 1 = IQSTB During the Data Word. 00 = Three-State IQSTB 01 = Enable IQSTB 1x = Auto Three-State Enable IQSTB (during time slot) 0 = True Data 1 = Inverted Data 00 = Three-State I 01 = Enable I 1x = Auto Three-State Enable I (during time slot) 0 = True Data 1 = Inverted Data 28 IQCLK Polarity 27 IQCLK Duty Cycle 26 IQCLK Duration IQCLK Three-State Control 25-24 23 IQSTB Polarity IQSTB Location IQSTB Three-State Control 22 21-20 19 I Polarity 18-17 I Three-State Control 16 Q Polarity 3-18 HSP50016 TABLE 9. INPUT AND OUTPUT FORMAT REGISTER (Continued) DESTINATION ADDRESS = 6 BIT POSITION 15-14 FUNCTION Q Three-State Control DESCRIPTION 00 = Three-State Q 01 = Enable Q 1x = Auto Three-State Enable Q (during time slot) 0 = Offset Binary 1 = Two's Complement I/QCLK Rate Counter Preload, Bits 12-0 = 212 ... 20. Range: 2 IQCLK Rate Counter Preload 1701. To calculate the value in this field use this equation: IQCLK Rate Counter Preload = [FLOOR[(HDF Decimation Factor x 4)/TSL] - 1]hex; where FLOOR(x) represents the integer part of x, and TSL is the decimal value of Control Word 3, bit 31-18. 13 Input Format 12-0 IQCLK Rate Counter Preload TABLE 10. PHASE OFFSET REGISTER DESTINATION ADDRESS = 7 BIT POSITION 39-37 36 35-14 13 12-11 FUNCTION Address Update Reserved Data FIR Accumulator Control 111 = Control Word 7 0 = Update Only This Control Register 1 = Update All Control Registers All Zeroes 0 = Normal Data Input 1 = Force Input Data to 8000 Hex. 00 = Normal Accumulation - The accumulator is reset on every FIR cycle. 01 = No Accumulation -The accumulator is disabled. 10 = Continuous Accumulation -The accumulator is not reset on every FIR cycle. This test mode was created to allow the user to perform the equivilent of a check sum test. A very long term test could be run and an accumulated output would yeild a specific numeric value. If the answer differed, the part is not functioning properly. 11 = Reserved 0 = Q carries Normal Data 1 = Q Strobes When Phase Generator Rolls Over 0 = Normal Output Response 1 = Force Outputs If Bit 9 = 1, Force IQCLK = Bit 8; Else Normal If Bit 9 = 1, Force IQSTB = Bit 7; Else Normal. If Bit 9 = 1, Force I = Bit 6; Else Normal. If Bit 9 = 1, Force Q = Bit 5; Else Normal. 0 = Sin Cos Generator Normal, 1 = Bypass Sin Cos Generator; Sin = Cos = 0.fffff (approximately 1) 0 = Scaling Multiplier Normal, 1 = Scale Factor = 1. Must be Zero for Proper Operation while Test Features are Enabled. If Bit = 0, DDC will Output Data Normally after a Reset, which will Include Unpredictable Data in Data RAMs. If Bit = 1, No Chip Output will Occur until Sufficient Data RAM Locations are Written. 0 = Normal Operation 1 = Disable Overflow Protection DESCRIPTION 10 9 8 7 6 5 4 3 2 1 0 Q Strobe on Roll Over Force Outputs IQCLK Forced Data IQSTB Forced Data I Forced Data Q Forced Data Sin/Cos Generator Bypass Scaling Multiplier Bypass Reserved Wait For RAM Full Disable Overflow Protection 3-19 HSP50016 HSP50016 supports two types of testing. Control Word 7 can be used to verify the operation of the circuit through the divide and conquer method. Setting the Enable Test Bit (Control Word 1, Bit 3) equal to a 1 enables the test features controlled by Control Word 7. (This bit is in Control Word 1 so that Word 7 does not have to be loaded if the test features are not being used.) The functions allowed by Control Word 7 are shown in Table 10. NOTE: Asserting bits 9 and 13 of Control Word 7 will put all outputs to a static mode. This may remove strobe enables or clocks used to read the data signals. This Test Mode was intended for interface evaluation at the board level. The DDC also has a Test Access Port (TAP). This port is fully conformant to IEEE Std. 1149.1 - 1990 - IEEE Standard Test Access Port and Boundary-Scan [2]. The TAP supports the following instructions: BYPASS, SAMPLE/PRELOAD, INTEST, EXTEST, RUNBIST and IDCODE. In addition, there are seven instructions called RDCNTLWD1-7, which read the contents of the control words over the TAP. The address bits and bit 36 are only used to determine the destination of data during loading; they are not stored, so they are not read out with the RDCNTLWD1-7 instruction. Where x(n) is the real input data sequence, = 2f, and c is the frequency of the signal generated by the SIN/COS Generator. For demonstration purposes let x(n) = cos(kn). The multiplication then becomes: u(n) = cos(kn)[cos(cn) - jsin(cn)] = 1/2[cos((k - c)n) + cos((k + c)n) - j(sin((k + c)n) - sin((k - c)n))] (EQ. 18) The signal u(n) is passed through a low pass filter; assuming that the filter passes the low frequency terms with no degradation and attenuates the high frequency terms completely, the filtering operation produces the output: v(n) = 1/2(cos((k - c)n) + jsin((k - c)n)) = 1/2ej(k - c)n (EQ. 19) When the magnitude of the input signal x(n) is one, the magnitude of v(n) is 1/2. Both the I and Q channels are multiplied by a factor of two to yield: w(n) = cos((k - c)n) + jsin((k - c)n) = ej(k - c)n. (EQ. 20) Summary To use the DDC in a down conversion application three items must be considered and designed to compliance. Solutions must satisfy all three items. 1. The Nyquist Sampling Rate for the bandwidth of interest FS 2BW, where BW is the bandwidth of interest. 2. The composite FIR/HDF double sided bandwidth, BW-3dB = 0.1375FS/R. 3. The desired serial output clock rate (total decimation, plus parallel to serial conversion rate increase). f S Length MIN IQCLK Frequency = ----------------------------------- - 1 (R FIR ) (R) NOTE: RFIR = 2 for real mode, 4 for all other modes. Figure 16 shows an HSP50016 in a single channel down conversion circuit. Notice that the input data is only 12 bits, so it is justified to the MSB of the DDC's input data. If a smaller sample width is used, it is recommended that the MSB of the data is input into DATA15. The unused bits are connected to ground. This alignment makes it easier to locate the position of the MSB in the output data. Note that the input is configured for offset binary arithmetic and the output is set up for I followed by Q, which enables the use of only one serial connection to the output processor. The serial data clock of the processor and the Control Clock of the DDC are driven by a TTL compatible oscillator. (IQCLK cannot be used for this purpose since its frequency is indeterminate until the DDC has been configured). Note that many processors provide a bit clock which eliminates the need for the external oscillator. Applications Down Conversion The primary spectral operation in the DDC is down conversion of an input signal to base band, see Figure 15. This process is done in two steps: multiplication of the input waveform by an internally generated quadrature sinusoid, i.e., modulation and lowpass filtering to attenuate the unwanted spectral components. The unwanted spectral components have two sources, the input signal and an artifact of the modulation process. The modulation process can be written as: u(n) = x(n)e-jc = x(n)[cos(c) - jsin(c)] (EQ. 17) - C A. INPUT SIGNAL SPECTRUM C B. DOWN CONVERSION AND FILTERING FIGURE 15. DOWN CONVERSION 3-20 HSP50016 12-BIT ADC VIN D11 . . CS . OE D0 A0 CONV . . . MICROPROCESSOR HSP50016 DATA15 . I . . IQCLK DATA4 IQSTB DATA0-3 CLK CDATA CCLK CSTB CS 5MHz OSCILLATOR DR CLKR FSR TABLE 13. SAMPLE FORMAT FOR CONTROL WORD 3 PHASE GENERATOR/OUTPUT TIME SLOT BIT POSITION 39-37 36 FUNCTION Address Update Reserved Time Slot Length Phase Offset DESCRIPTION 011 = Control Word 3. 1 = Control Register Update. All Zeroes. All Zeroes. All Zeroes. DX CLKX FSX 35-32 31-18 17-0 0111 0000 0000 0000 0000 0000 0000 0000 0000 0000 TABLE 14. SAMPLE FORMAT FOR CONTROL WORD 4 PHASE GENERATOR/HDF/OUTPUT FIGURE 16. CIRCUIT FOR SINGLE CHANNEL OPERATION BIT POSITION 39-37 36 35-33 32 31 30-7 TABLE 11. SAMPLE FORMAT FOR CONTROL WORD 1 PHASE GENERATOR/TEST ENABLE BIT POSITION 39-37 36 35-4 FUNCTION Address Update Minimum Phase Increment DESCRIPTION 001 = Control Word 1. 1 = Control Register Update. Minimum Phase Increment Computed according to [fC/fS] 233. 0 = Test Features Disabled. 001 = Normal Mode. 0 Spectral Reverse 6-1 FUNCTION Address Update Reserved Up Convert Real Mode Delta Phase Increment Shift DESCRIPTION 100 = Control Word 4. 1 = Control Register Update. All Zeroes. 0 = Do Not Up convert. 0 = Complex Mode. All Zeroes. 37 = Decimal 55, the Shift Corresponding to HDF Decimation by 16. 0 = No Spectral Reversal An example of the control word contents for this mode of operation is given in Tables 11 through 17. In this setup, the DDC has been configured for a constant down conversion frequency, decimation by 64 and Test Features disabled. Bit fields of three bits or less are in binary notation; longer fields are in hexadecimal. Control Words Zero and Seven are not used. 1001 0000 0000 0000 0000 0000 0000 0000 0110 1110 TABLE 15. SAMPLE FORMAT FOR CONTROL WORD 5 HDF/OUTPUT BIT POSITION 39-37 36 35-21 20-5 4-3 2-1 0 FUNCTION Address Update HDF Decimation Counter Preload Scaling Multiplier Gain Output Format Number of Output Bits Output Sense DESCRIPTION 101 = Control Word 5. 1 = Control Register Update. F = Decimation by 16 in HDF. 8000 = Scaling Multiplier Gain of 1. 00 = Two's Complement. 00 = 16-Bits. 1 = MSB First. 3 2-0 Test Enable Phase Generator Mode 0011 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0001 TABLE 12. SAMPLE FORMAT FOR CONTROL WORD 2 PHASE GENERATOR BIT POSITION 39-37 36 35-32 31-0 FUNCTION Address Update Reserved Maximum Phase Increment DESCRIPTION 010 = Control Word 2. 1 = Control Register Update. All Zeroes. All Zeroes. 1011 0000 0000 0001 1111 0000 0000 0000 0000 0000 0101 0000 0000 0000 0000 0000 0000 0000 0000 0000 3-21 HSP50016 TABLE 16. SAMPLE FORMAT FOR CONTROL WORD 6 OUTPUT BIT POSITION 39-37 36 35 34-29 28 27 26 25-24 23 22 21-20 19 18-17 16 15-14 13 12-0 FUNCTION Address Update I followed by Q Time Slot IQCLK Polarity DESCRIPTION 110 = Control Word 6. 1 = Control Register Update. 1 = I and Q Data Output on I Pin. Time Slot Number = 0. 0 = Data Stable on Rising Edge of IQCLK. sideband from aliasing onto the other sideband when the real part of the output signal is taken. The spectrum of a quadrature signal which has been over sampled by 2 is shown in Figure 17A. This represents the output of the filters. As described in the previous paragraph, the oversampling is a necessary feature of this process, since the final signal will occupy twice the bandwidth of the filter output. To prevent aliasing upon taking the real part of the signal, it is necessary to perform an up conversion by f"/4, where f" is the decimated sample frequency. (Note that fs is defined as the input sampling frequency, f' is the input sampling frequency divided by the HDF decimation rate R, and f" is f' divided by the FIR decimation rate. f'' is the FIR output sampling rate). The up conversion function is: ej2nf''/4f'' = ejn/2 (EQ. 21) IQCLK Duty Cycle 1 = IQCLK Duty Cycle is 50%. IQCLK Duration IQCLK ThreeState Control IQSTB Polarity IQSTB Location IQSTB Three-State I Polarity I Three-State Control Q Polarity Q Three-State Control Input Format IQCLK Rate 1 = Active Continuously. 01 = Enable IQCLK. 0 = IQSTB Active High. 0 = IQSTB Active Prior to the Beginning of the Data Word. 01 = Enable IQSTB. 0 = I Output Active High. 01 = Enable I. 0 = Q Output Active High. 00 = Disable Q. 1 = Two's complement. All Zeroes = CLK Used to Clock Output Bits. For n = 0, 1, 2, 3, 4,... the output values of the local oscillator in rectangular representation are: 1 + 0j, 0 + j, -1 + 0j, 0 - j, 1 + 0j,.... Since the real half of the complex multiplication of the local oscillator values by the filtered signal values (the desired output is the real part of the product) require only trivial operations, this up conversion is done in the Formatter. Figure 17B shows the signal spectrum after up conversion. Figure 17C shows the spectrum of the real output signal. Continuing with the single tone example from the previous section, the quadrature signal output from the FIR filters is: w(n) = cos((k - c)n) + jsin((k - c)n) = ej(k - c)n (EQ. 22) 1101 1000 0000 1101 0001 0010 001X XXXX XXXX XXXX Multiplying w(n) by the up convert function and summing the result is equivalent to the output sequence: y(n) = 1 x cos((k - c)n), y(n+1) = j x jsin((k - c)(n+1)), y(n+2) = -1 x cos((k - c)(n+2)), y(n+3) = -j x jsin((k - c)(n+3)), y(n+4) = 1 x cos((k - c)(n+4)),... y = cos((k - c)n), -sin((k - c)(n+1)), -cos((k - c)(n+2)), sin((k - c)(n+3)), cos((k - c)(n+4)),... Or: y = RE(w(n)), - IM(w(n+1)), - RE(w(n+2)), IM(w(n+3)), RE(w(n+4)),... Since |ejn/2| = 1 and |w(n)| = 1, no further magnitude corrections are required. The setup for this application is similar to that of the down conversion circuit given above, except the Output Formatter is set for Real Mode (Bit 31 in Control Word 4). This bit configures the part for up conversion by f"/4 and summing of the real and imaginary parts of the filter output. (EQ. 23) TABLE 17. SUMMARY OF CONTROL WORDS FOR THE EXAMPLE CONTROL WORD 0 1 2 3 4 5 6 7 HEX VALUE 0000000000 3XXXXXXXX1 5000000000 7000000000 900000006E B001F00000 D80D12XXXX 0000000000 Quadrature To Real Conversion After the input data has been processed by the DDC, the output can be converted into a real signal if desired. In that case, the baseband centered quadrature signal is upcobaseband. The real part of the upconverted signal is taken as the output. To satisfy the Nyquist criteria, the sample rate of the resulting signal must be at least twice the minimum sample rate of the I and Q components of the quadrature signal. This prevents one 3-22 HSP50016 fS = f1'R f1' = 2f" -f"/2 -f' 4 -fS 4R -f"/4 -f' 8 -fS 8R 0 f"/4 f' 8 fS 8R f"/2 f' 4 fS 4R -f"/2 -f' 4 -fS 4R -f"/4 -f' 8 -fS 8R 0 f"/4 f' 8 fS 8R f"/2 f' 4 fS 4R A. OUTPUT OF FIR FILTERS: SIGNAL OVERSAMPLED BY 2 B. FIRST OPERATION IN FORMATTER: UP CONVERT BY SAMPLE FREQUENCY / 4 -f"/2 -f' 4 -fS 4R -f"/4 -f' 8 -fS 8R 0 f"/4 f' 8 fS 8R f"/2 f' 4 fS 4R C. SECOND OPERATION IN FORMATTER: I OUTPUT = I + Q FIGURE 17. QUADRATURE TO REAL CONVERSION OF AN OUTPUT SIGNAL Up Conversion by f"/2 This operation allows the user to exchange the positions of the upper and lower halves of a down converted signal while leaving each half unchanged. Quadrature up conversion by f"/2 is performed by multiplying the output signal by ej2nf''/2 = cos(2pnf"/2) + j sin(2pnf"/2). When sampled at a rate of f", cos(2pnf"/2) takes on the values 1, -1, 1, -1,... and sin(2pnf"/2) always = 0. Thus, the up convert LO sequence is: ejn = 1 + j0, -1 + j0, 1 + j0, ... (EQ. 24) The Formatter contains the circuitry to shift the quadrature output spectrum up by one half of the output sample frequency f". This operation is independent of the function of the Phase Generator and Mixer. The spectra of the outputs of the Filter and Formatter are shown in Figure 18. The setup is identical to the down conversion configuration, except that the Up Convert Bit is set in Control Word 4. This sequence is multiplied by the output of the I and Q branches of the filter: w(n) = cos((k - c)n) + jsin((k - c)n) = ej(k - c)n, (EQ. 25) -f"/2 -f"/4 0 f"/4 f"/2 A. OUTPUT OF FIR FILTERS yielding an output sequence: y = (RE(w(n)), IM(w(n))), -RE(w(n+1)), - IM(w(n+1))), RE(w(n+2)), IM(w(n+2))), ... (EQ. 26) -f"/2 -f"/4 0 f"/4 f"/2 B. FILTER OUTPUT UP CONVERTED BY OUTPUT SAMPLE FREQUENCY / 2 FIGURE 18. UP CONVERSION BY F" / 2 3-23 HSP50016 Quadrature Spectral Reversal Spectral reversal is often used to negate a spectral reversal which has occurred due to a previous operation in the processing chain. Examples of this are spectral reversal in an analog down conversion or in a constructive aliasing operation. The DDC gives the user the ability to convert the signal to baseband in either forward or reverse fashion. Quadrature spectral reversal is achieved by translating the lower sideband of the input to baseband rather than the upper sideband. This is implemented in the DDC by mixing the input signal with ej2fcn - that is, up converting the input rather than down converting it. The resulting signal is: u(n)= x(n)ej2fcn = x(n)[cos(cn) + jsin(cn)] Assuming x(n) = cos(kn), (n) = cos(kn)[cos(cn) + jsin(cn)] = [cos((k - c)n) + cos((k + c)n) + j(sin((k + c)n) - sin((k - c)n))] (EQ. 28) (EQ. 27) quadrature to real conversion. The output spectrum is shown in Figure 20. -f"/2 -f"/4 0 f"/4 f"/2 A. OUTPUT OF FILTERS: SIGNAL OVERSAMPLED BY 2 -f"2 -f"/4 0 f"/4 f"/2 B. FIRST OPERATION IN FORMATTER: UP CONVERT BY SAMPLE FREQUENCY / 4 -f"/2 -f"/4 0 f"/4 f"/2 C. SECOND OPERATION IN FORMATTER: I OUTPUT = I + Q After quadrature filtering and correcting for the gain of 1/2, we have: w(n) = cos((k - c)n) - jsin((k - c)n) = cos(-(k - c)n) + jsin(-(k - c)n) = cos((c - k)n) + jsin((c - k)n) = ej(c- k)n (EQ. 29) FIGURE 20. QUADRATURE TO REAL CONVERSION OF AN OUTPUT SIGNAL The setup for this application is similar to that of down conversion, except in Control Word 4, where the Spectral Reverse and Real Output bits are set to one. The appropriate spectral plots are shown in Figure 19. In up conversion, the sine output of the SIN/COS Generator is negated so that the vector output of the Local Oscillator rotates counter clockwise. This is implemented by setting the Spectral Reverse bit in Control Word 4 to a one. Otherwise, the setup for this mode is the same as the one for down conversion. High Decimation Filter Only The DDC can be operated as a single high decimation filter. This is done by setting the Phase Generator to Filter Only and the Minimum Phase Increment and Phase Offset to 0. This multiplies the incoming data stream by a constant hexadecimal 3FFFF in the I channel and 0 in the Q channel. The HDF Section of the circuit requires a minimum decimation rate of 16 to allow sufficient time for the FIR to compute its response. This mode of operation implements a filter which has a decimation rate from 64 to 131,072. The frequency response is shown in Figures 7, 8 and 9. Only the I output has valid data in this mode; the Q output should be set to high impedance state to reduce circuit noise. - C A. INPUT SIGNAL SPECTRUM C Multichannel Operation B. UP CONVERSION AND FILTERING FIGURE 19. UP CONVERSION OF FILTER OUTPUT SIGNAL Real Spectral Reversal Real spectral reversal is simply quadrature spectral reversal with quadrature to real conversion in the Formatter. The up converted and filtered signal w(n) is upconverted again by f"/4 in the Formatter. Each sideband of the result is spectrally reversed from the sidebands that would have been produced by down conversion with 3-24 Several DDCs can be placed in parallel with each one operating on a different frequency band. To minimize wiring, their outputs can be configured so that they are connected over a common serial bus. Each DDC is assigned a time slot number (Control Word 6) and a time slot length (Control Word 3). Each DDC in turn controls the bus for long enough to output its data, then relinquishes the bus. The time slot assignment and length are programmed at configuration time. Up to 64 chips can be multiplexed in this manner. HSP50016 Figure 21 shows a Block Diagram of this configuration. The DDCs are configured by the microprocessor by first writing a logical 0 to its Chip Select line. The control words are written to that part in any order. When the part has been configured, CS is written high again, and the next part is configured in the same manner. Collisions are prevented by programming each DDC with a unique Time Slot number, which holds its output from 0 to 63 output word times before transmission. Each part also has a Time Slot Length, whose minimum value is given in Equation 8. Note that a value greater than the minimum can be used to give the processor time to operate on the data DATA FROM A/D HSP50016 I DATA0-15 IQCLK IQSTB IQSTRT CLK CDATA CCLK CSTB CS MICROPROCESSOR When operating a set of HSP50016s in the Multiple Channel Operation Mode, the two control signals that ensure proper time slot operation are: CS and RESET. The CS allows unique Control Word loading of each DDC. The RESET synchronizes all of the DDC's to the start of the first time slot. TIME SLOT 0 DDC 0 TIME SLOT 1 TIME SLOT N-1 DDC 1 DDC N-1 FIGURE 22. TIMING FOR MULTIPLE CHANNEL OPERATION (AUTO THREE-STATE) CHIP SELECT DECODER A0-15 R/W STRB NOTE: In this mode, it was anticipated that parallel DDC's would be programmed identically, except for the NCO (L.O.) frequency and Time Slot Number. This implies identical HDF Decimation factors, Time Slot Length's, Number of Output Bits, Output Mode are identical in all DDCs. This means that the output rate of all DDC HDFs, FIRs and Parallel to Serial Converters are identical. The DDC keeps an internal count of the number of IQCLK periods that have transpired since the rising edge of RESET. The internal counter of each DDC is set to enable the serial output at the time slot number assigned to that DDC. The count is based on the time slot length, number of output bits, HDF decimation, and Output Mode programmed to that part. NOTE: In the Multiple Channel Operation Mode, all the time slot lengths should be set to the same value to avoid output signal contention. The time slot length should be equal to the largest "minimum time slot length" as calculated by Equation 15, for every DDC in the multichannel arrangement. Note that Equation 8 is in IQCLK periods, not CLK periods. Equations 7 and 9 will be helpful in making the translation to CLK periods. This mode does not require that all of the time slots be used (assigned to a DDC). If only two parts were used and the maximum time signal isolation was desired, one could assign the first signal time slot 31 and the second signal time slot 63. This would ensure that the maximum separation in time occurred. It is the designers responsibility to ensure that the output rate, including the decimation is consistent with the time allotted to output each signal. HSP50016 I DATA0-15 IQCLK IQSTB CLK SYSTEM CLOCK IQSTRT CDATA CCLK CSTB CS DX CLKX FSX OSCILLATOR DR CLKR FSR FIGURE 21. CIRCUIT FOR MULTIPLE CHANNEL OPERATION (AUTO THREE-STATE) The corresponding Configuration Register setup is similar to that of single channel down conversion, except for the Auto Three-State fields. In this example, the first DDC in the chain is set to drive IQCLK; the others have this output set for high impedance. (It makes no difference which DDC is chosen to be the one to drive IQCLK, but it must be active continuously). The unused outputs are put in their high impedance condition on the other DDCs to minimize power consumption. Note also that this example shows all DDCs in I followed by Q Mode so that only one data line to the microprocessor is necessary. Figure 22 gives the timing of the output data. 3-25 HSP50016 Let's return to the clock calculation example found in the Output Formatter, and add the requirement of 4 time slots. The calculations in the Example Clock Calculation Section remain true, but step 8 must be added: 8. Now lets consider the multichannel timing. Each channel must output the data at no less than 1.725MHz to get all the I/Q data out in the allocated time for the assigned time slot. Time margin is created when the output is clocked out at a higher rate. Because each channel is outputting data in only one of four channels, the effective output rate for each channel is 1.725MHz /4 = 431.25kHz, even though the part is outputting data 1.7MHz in every time slot. . . . . . . . . . . Effective Channel Output Rate = 431.25kHz Alternatively, the processor can request data from each of the DDCs asynchronously. In this setup, Requested Output Mode is used. The Data Concentrator polls each channel individually and is responsible for ensuring that each channel is polled before the output data is lost. The Data Concentrator is a custom circuit designed by the user. A Block Diagram of such a system is shown in Figure 23. The interface between the controller and the DDCs has been omitted for the sake of clarity. SYSTEM CLOCK DATA CONCENTRATOR MICROPROCESSOR A0-15 D0 R/W STRB DATA FROM A/D HSP50016 DATA0-15 I IQCLK IQSTB IQSTRT CLK HSP50016 DATA0-15 I IQCLK IQSTB IQSTRT CLK FIGURE 23. CIRCUIT FOR MULTIPLE CHANNEL OPERATION (REQUESTED OUTPUT) References [1] Hogenauer, Eugene V., An Economical Class of Digital Filters for Decimation and Interpolation, IEEE Transactions on Acoustics, Speech and Signal Processing, April 1981. [2] IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1 - 1990. 3-26 HSP50016 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Information Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) PLCC Package. . . . . . . . . . . . . . . . . . . 35 N /A Maximum Junction Temperature PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC Operating Conditions Operating Voltage Range. . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V Operating Temperature Range . . . . . . . . . . . . . . . . . . . 0oC to 70oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65,000 Gates CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications PARAMETER Power Supply Current VCC = 5.0V 5%, TA = 0o to 70oC SYMBOL ICCOP TEST CONDITIONS VCC = Max, CLK Frequency 52.6MHz Notes 2, 3 VCC = Max, CLK Frequency 76.9MHz Notes 2, 3 MIN -500 -10 -10 2.0 3.0 2.6 MAX 394 577 500 10 10 10 0.8 0.4 10 10 UNITS mA mA A A A A V V V V V pF pF Standby Power Supply Current Input Leakage Current ICCSB II VCC = Max, Outputs Not Loaded VCC = Max, Input = 0V or VCC TMS, TDI, TRST VCC = Max, Input = 0V or VCC All other inputs Output Leakage Current Logical One Input Voltage Logical Zero Input Voltage Logical One Input Voltage: CLK, TRST Logical One Output Voltage Logical Zero Output Voltage Input Capacitance Output Capacitance NOTES: IO VIH VIL VIHC VOH VOL CIN COUT VCC = Max, Input = 0V or VCC VCC = Max VCC = Min VCC = Max IOH = -5mA, VCC = Min IOL = 5mA, VCC = Min CLK Frequency 1MHz All measurements referenced to GND. TA = 25oC, Note 4 2. Power supply current is proportional to frequency. Typical rating is 7.5mA/MHz. Note that operation at maximum clock frequency will exceed maximum junction temperature of device. Use of a heat sink and/or air flow is required under these conditions: Recommended heat sink is EG&G Wakefield D10650-40. 3. Output load per test circuit and CL = 40pF. 4. Not tested, but characterized at initial design and at major process/design changes. AC Electrical Specifications PARAMETER CLK Period CLK High CLK Low Setup Time DATA0-15 to CLK Hold Time DATA0-15 from CLK RESET Pulse Width RESET, IQSTRT Setup Time from CLK VCC = 5.0V 5%, TA = 0o to 70oC, (Note 5) -52(52.6)MHz SYMBOL tCP tCH tCL tDS tDH tRL tRS Note 6 NOTES MIN 19 7 7 10 1 tCP+11 10 MAX -75(76.9)MHz MIN 13 5 5 7 1 tCP+8 7 MAX UNITS ns ns ns ns ns ns ns 3-27 HSP50016 AC Electrical Specifications PARAMETER RESET, IQSTRT Hold Time to CLK CLK to I, Q, IQSTB, IQCLK Delay CCLK Period CCLK High CCLK Low CDATA, CSTB, CS Setup to CCLK CDATA, CSTB, CS Hold from CCLK CCLK Low Setup to CLK CCLK High Hold from CLK TCK Period TCK High TCK Low TRST Pulse Width TCK to TDO, Data Delay Setup Time On All Inputs to TCK Hold Time On All Inputs from TCK TCK Setup Time to CLK TCK Hold Time from CLK Output Enable Time from CLK Output Disable Time from CLK Output Enable Time from TCK Output Disable Time from TCK Output Rise, Fall Time NOTES: 5. AC tests performed with CL= 40pF, IOL = 5mA, and IOH = -5mA. Input reference level for CLK, TRST is 2.0V, all other inputs 1.5V. Test VIH = 3.0V, VIHC = 4.0V, VIL = 0V; VOH = VOL = 2.5V. 6. These are asynchronous inputs; setup and hold times must only be maintained in order to predict which clock cycle they take effect internally. 7. Timing must only be maintained when Update bit is active in control word data being loaded. 8. Special Timing relationship between TCK and CLK is required for Test Instructions RUNBIST, EXTEST and INTEST. 9. All inputs except TRST, and only when TCK is driving internal clock. 10. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. VCC = 5.0V 5%, TA = 0o to 70oC, (Note 5) (Continued) -52(52.6)MHz SYMBOL tRH tDO tCCP tCCH tCCL tCDS tCDH tCLS tCHH tTCP tTH tTL tTRL tTDO tATS tATH tTCS tTCH tOE tOD tTOE tTOD tRF Note 9 Note 9 Note 8 Note 8 Note 10 Note 10 Note 10 Note 10 Note 10 Notes 6, 7 Notes 6, 7, 10 Note 8 NOTES Note 6 MIN 1 100 40 40 30 30 30 30 100 40 40 100 30 30 30 30 MAX 15 30 18 18 32 32 5 -75(76.9)MHz MIN 1 100 40 40 30 30 30 30 100 40 40 100 30 30 30 30 MAX 12 30 12 12 32 32 5 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns AC Test Load Circuit DUT S1 CL (NOTE) SWITCH S1 OPEN FOR ICCSB AND ICCOP IOH 2.5V IOL EQUIVALENT CIRCUIT NOTE: Test head capacitance. 3-28 HSP50016 Waveforms tCP tCH CLK tCL tDS DATA0-15, IQSTRT tDH tRH tRL RESET tRS tDO I, Q, IQSTB, IQCLK tOE 2.7V I, Q, IQSTB, IQCLK 2.3V tOD I, Q, IQSTB, IQCLK tCLS CCLK tCHH tTCS TCK tTCH FIGURE 24. TIMING RELATIVE TO CLK tCCP tCCH tCCL CCLK tCDS CDATA, CSTB, CS tCDH FIGURE 25. TIMING RELATIVE TO CCLK 3-29 HSP50016 Waveforms (Continued) tTCP tTH TCK tTL TRST tTRL tTDO TDO, I, Q, IQSTB, IQCLK tATS ALL INPUTS tATH tTOE 2.7V TDO, I, Q, IQSTB, IQCLK 2.3V tTOD TDO, I, Q, IQSTB, IQCLK FIGURE 26. TIMING RELATIVE TO TCK tRF tRF 2.0V 0.8V FIGURE 27. OUTPUT RISE AND FALL TIMES All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 3-30 |
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